A full-T cross is a time-slot level cross, which refers to that, as for a multi-channel and multi-slot interleaving input service, a cross device can cross service data of the input service of any channel and any time slot to any channel and any time slot of an output service without blocking. For example, as for a Synchronous Digital Hierarchy (SDH) application, the structure of a Synchronous Transport Module (STM)-1 frame is a frame of 9 lines and 270 columns, while the structure of an STM-N frame is interleaved by N STM-1 frames according to time slots (byte interleave herein).
During the conception the present invention, the inventor finds that the prior art has at least the following drawbacks: At present, the two dominant methods for implementing the full-T cross are respectively: using a Random Access Memory (RAM) to implement the full-T cross, which directly leads to the expansion of the chip size due to increasing demand for on-chip RAM; and using a Multiplexer (MUX) to implement the full-T cross, which brings great difficulty to the layout and wiring at the back end of the chip due to excessive MUXs and interconnection lines, and eventually leads to the expansion of the chip size as well. It can be seen that, with the improvement of the capacity of the current full-T cross chip, the size of the chip is also increasing, which directly leads to the increase in the costs and power consumption of the chip.